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rf pll frequency synthesizers adf4110/adf4111/adf4112/adf4113 rev. c in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . features adf41 10: 5 50 mhz; a d f411 1 : 1.2 g hz; adf4 112: 3. 0 gh z; adf41 13: 4. 0 g hz 2.7 v to 5.5 v p o wer supply separate charge pump supply (v p ) allows extended t u ning voltage in 3 v s y stems programmable dua l -modul us prescaler 8/9, 1 6 /17, 32/33, 64/65 programmable charge pump currents programmable antibacklash p u lse wi dth 3-wire seri al in terface analo g and d i gital lo ck de tect hardware and software power-down mode applications base stations f o r wireless radi o (gsm, pcs, dcs, cdma, wcdma) wireless han d s e ts (gsm, p c s, dcs, cdma, w c dma) wireless lans communications test eq uipm ent catv equipment general d e scription the ad f4110 f a mil y o f f r eq uen c y syn t h e sizers ca n be us e d t o im ple m e n t lo ca l o s ci l l a t o r s i n t h e u p con v ersio n a nd do w n con- versio n s e c t io n s o f wir e less r e ce i v ers a nd t r a n s m i t ters. t h e y c o ns i s t of a l o w noi s e d i g i t a l pf d ( p h a s e f r e q u e nc y d e te c t or ) , a pre c i s i o n c h ar g e pu m p , a pro g r a m m a bl e re f e re nc e d i v i d e r , p r o g r a mma b l e a an d b co u n te rs, a n d a d u a l - m o d u l us p r es ca le r (p/p + 1). t h e a (6-b i t ) and b (13-b i t) co un t e rs, in co n j un c t io n wi t h t h e d u al - m o d u l us p r es cale r (p/p + 1), im plem e n t an n divider (n = bp + a). i n ad di t i on, t h e 14 -b i t r e fer e n c e co u n ter (r co un t e r) al lo ws s e le c t ab le r e fin f r e q uen c ies a t t h e p f d in p u t. a com p le t e p h as e - lo ck e d lo o p (p ll) ca n be im p l e m e n t e d if th e sy n t h e sizer is us ed wi th an ext e r n al lo o p f i l t er a nd v o l t a g e c o n t r o ll ed osc i lla t o r (v co ). c o n t r o l o f al l th e o n -c hi p r e g i s t ers is via a sim p le 3-wir e in t e r f ace . the de v i ces o p er a t e wi t h a p o w e r s u p p l y ra n g in g f r o m 2.7 v to 5.5 v and can b e p o w e r e d do w n w h e n n o t i n us e. functional bloc k dia g ram n = bp + a function latch prescaler p/p +1 13-bit b counter 6-bit a counter 14-bit r counter 24-bit input register r counter latch a, b counter latch phase frequency detector av dd sd out 19 13 14 22 sd out from function latch dgnd agnd ce rf in a rf in b le data clk ref in cpgnd v p dv dd av dd lock detect adf4110/adf4111 adf4112/adf4113 6 load load reference charge pump m3 m2 m1 high z mux muxout cp r set current setting 2 cpi3 cpi2 cpi1 cpi6 cpi5 cpi4 current setting 1 03496-0-001 f i gur e 1 . f u nctio n al bl oc k dia g r a m
adf4110/adf4111/a df4112/adf4113 rev. c | page 2 of 28 table of contents specifications..................................................................................... 3 timing characteristics..................................................................... 5 absolute maximum ratings............................................................ 6 transistor count........................................................................... 6 esd caution.................................................................................. 6 pin configurations and function descriptions ........................... 7 typical performance characteristics ............................................. 8 circuit description......................................................................... 12 reference input section............................................................. 12 rf input stage............................................................................. 12 prescaler (p/p + 1)...................................................................... 12 a and b counters ....................................................................... 12 r counter .................................................................................... 12 phase frequency detector (pfd) and charge pump............ 13 muxout and lock detect........................................................... 13 input shift register .................................................................... 13 function latch............................................................................ 19 initialization latch ..................................................................... 20 device programming after initial power-up ......................... 20 resynchronizing the prescaler output.................................... 21 applications..................................................................................... 22 local oscillator for gsm base station transmitter .............. 22 using a d/a converter to drive the r set pin......................... 23 shutdown circuit ....................................................................... 23 wideband pll ............................................................................ 23 direct conversion modulator .................................................. 25 interfacing ................................................................................... 26 pcb design guidelines for chip scale package .................... 26 outline dimensions ....................................................................... 27 ordering guide............................................................................... 28 revision history 3/04data sheet changed from rev. b to rev. c. updated format..............................................................universal changes to specifications ............................................................ 2 changes to figure 32.................................................................. 22 changes to the ordering guide................................................ 28 3/03data sheet changed from rev. a to rev. b. edits to specifications .................................................................. 2 updated outline dimensions ........................................ 24 1/01data sheet changed from rev. 0 to rev. a. changes to dc specifications in b version, b chips, unit, and test conditions/comments columns................. 2 changes to absolute maximum rating..................................... 4 changes to fr in a function test ................................................ 5 changes to figure 8...................................................................... 7 new graph addedtpc 22....................................................... 9 change to pd polarity box in table v..................................... 15 change to pd polarity box in table vi ................................... 16 change to pd polarity paragraph ............................................ 17 addition of new material (pcb design guidelines for chipCscale package) ........... 23 replacement of cp-20 outline with cp-20 [2] outline........ 24
adf4110/adf4111/a df4112/adf4113 rev. c | page 3 of 28 specifications av dd = dv dd = 3 v 10%, 5 v 10%; av dd v p 6.0 v; agnd = dgnd = cpgnd = 0 v; r set = 4.7 k?; dbm referred to 50 ?; t a = t min to t max , unless otherwise noted. operating temperature range is as follows: b version: ?40c to +85c. table 1. parameter b version b chips 1 unit test conditions/comments rf characteristics (3 v) see figure 29 for input circuit. rf input sensitivity ?15/0 ?15/0 dbm min/max rf input frequency adf4110 80/550 80/550 mhz min/max for lo wer frequencies, ensure slew rate (sr) > 30 v/s. adf4110 50/550 50/550 mhz min/max input level = ?10 dbm. adf4111 0.08/1.2 0.08/1.2 ghz min/max for lo wer frequencies, ensure sr > 30 v/s. adf4112 0.2/3.0 0.2/3.0 ghz min/max for lo wer frequencies, ensure sr > 75 v/s. adf4112 0.1/3.0 0.1/3.0 ghz min/ max input level = ?10 dbm. adf4113 0.2/3.7 0.2/3.7 ghz min/max input le vel = ?10 dbm. for lower frequencies, ensure sr > 130 v/s. maximum allowable prescaler output frequency 2 165 165 mhz max rf characteristics (5 v) rf input sensitivity ?10/0 ?10/0 dbm min/max rf input frequency adf4110 80/550 80/550 mhz min/max for lower frequencies, ensure sr > 50 v/s. adf4111 0.08/1.4 0.08/1.4 ghz min/max for lo wer frequencies, ensure sr > 50 v/s. adf4112 0.1/3.0 0.1/3.0 ghz min/max for lo wer frequencies, ensure sr > 75 v/s. adf4113 0.2/3.7 0.2/3.7 ghz min/max for lo wer frequencies, ensure sr > 130 v/s. adf4113 0.2/4.0 0.2/4.0 ghz min/ max input level = ?5 dbm maximum allowable prescaler output frequency 2 200 200 mhz max refin characteristics refin input frequency 5/104 5/104 mhz min/max for f < 5 mhz, ensure sr > 100 v/s. reference input sensitivity 0.4/av dd 0.4/av dd v p-p min/max av dd = 3.3 v, biased at av dd /2. see note 3. 3.0/av dd 3.0/av dd v p-p min/max av dd = 5 v, biased at av dd /2. see note 3. refin input capacitance 10 10 pf max refin input current 100 100 a max phase detector frequency 4 55 55 mhz max charge pump i cp sink/source programmable (see table 9). high value 5 5 ma typ with r set = 4.7 k? low value 625 625 a typ absolute accuracy 2.5 2.5 % typ with r set = 4.7 k? r set range 2.7/10 2.7/10 k? typ see table 9. i cp 3-state leakage current 1 1 na typ sink and source current matching 2 2 % typ 0.5 v v cp v p C 0.5 v. i cp vs. v cp 1.5 1.5 % typ 0.5 v v cp v p C 0.5 v. i cp vs. temperature 2 2 % typ v cp = v p /2. logic inputs v inh , input high voltage 0.8 dv dd 0.8 dv dd v min v inl , input low voltage 0.2 dv dd 0.2 dv dd v max i inh /i inl , input current 1 1 a max c in , input capacitance 10 10 pf max logic outputs v oh , output high voltage dv dd C 0.4 dv dd C 0.4 v min i oh = 500 a. v ol , output low voltage 0.4 0.4 v max i ol = 500 a.
adf4110/adf4111/a df4112/adf4113 rev. c | page 4 of 28 parameter b version b chips 1 unit test conditions/comments power supplies av dd 2.7/5.5 2.7/5.5 v min/v max dv dd av dd av dd v p av dd /6.0 av dd /6.0 v min/v max av dd v p 6.0 v. see figure 25 and figure 26. i dd 5 (ai dd + di dd ) adf4110 5.5 4.5 ma max 4.5 ma typical adf4111 5.5 4.5 ma max 4.5 ma typical adf4112 7.5 6.5 ma max 6.5 ma typical adf4113 11 8.5 ma max 8.5 ma typical i p 0.5 0.5 ma max t a = 25c low power sleep mode 1 1 a typ noise characteristics adf4113 normalized phase noise floor 6 ?215 ?215 dbc/hz typ phase noise performance 7 @ vco output adf4110: 540 mhz output 8 ?91 ?91 dbc/hz typ @ 1 khz offset and 200 khz pfd frequency adf4111: 900 mhz output 9 ?87 ?87 dbc/hz typ @ 1 khz offset and 200 khz pfd frequency adf4112: 900 mhz output 9 ?90 ?90 dbc/hz typ @ 1 khz offset and 200 khz pfd frequency adf4113: 900 mhz output 9 ?91 ?91 dbc/hz typ @ 1 khz offset and 200 khz pfd frequency adf4111: 836 mhz output 10 ?78 ?78 dbc/hz typ @ 300 hz offset and 30 khz pfd frequency adf4112: 1750 mhz output 11 ?86 ?86 dbc/hz typ @ 1 khz offset and 200 khz pfd frequency adf4112: 1750 mhz output 12 ?66 ?66 dbc/hz typ @ 200 hz offset and 10 khz pfd frequency adf4112: 1960 mhz output 13 ?84 ?84 dbc/hz typ @ 1 khz offset and 200 khz pfd frequency adf4113: 1960 mhz output 13 ?85 ?85 dbc/hz typ @ 1 khz offset and 200 khz pfd frequency adf4113: 3100 mhz output 14 ?86 ?86 dbc/hz typ @ 1 khz offset and 1 mhz pfd frequency spurious signals adf4110: 540 mhz output 9 ?97/?106 ?97/?106 dbc typ @ 200 khz/400 khz and 200 khz pfd frequency adf4111: 900 mhz output 9 ?98/?110 ?98/?110 dbc typ @ 200 khz/400 khz and 200 khz pfd frequency adf4112: 900 mhz output 9 ?91/?100 ?91/?100 dbc typ @ 200 khz/400 khz and 200 khz pfd frequency adf4113: 900 mhz output 9 ?100/?110 ?100/?110 dbc typ @ 200 khz/400 khz and 200 khz pfd frequency adf4111: 836 mhz output 10 ?81/?84 ?81/?84 dbc typ @ 30 khz/60 khz and 30 khz pfd frequency adf4112: 1750 mhz output 11 ?88/?90 ?88/?90 dbc typ @ 200 khz/400 khz and 200 khz pfd frequency adf4112: 1750 mhz output 12 ?65/?73 ?65/?73 dbc typ @ 10 khz/20 khz and 10 khz pfd frequency adf4112: 1960 mhz output 13 ?80/?84 ?80/?84 dbc typ @ 200 khz/400 khz and 200 khz pfd frequency adf4113: 1960 mhz output 13 ?80/?84 ?80/?84 dbc typ @ 200 khz/400 khz and 200 khz pfd frequency adf4113: 3100 mhz output 14 ?80/?82 ?82/?82 dbc typ @ 1 mhz/2 mhz and 1 mhz pfd frequency 1 the b chip specifications are given as typical values. 2 this is the maximum operating frequency of the cmos counters. the prescaler value should be chosen to ensure that the rf input is divided down to a frequency that is less than this value. 3 ac coupling ensures av dd /2 bias. see figure 33 for a typical circuit. 4 guaranteed by design. 5 t a = 25c; av dd = dv dd = 3 v; p = 16; sync = 0; dly = 0; rf in for adf4110 = 540 mhz; rf in for adf4111, adf4112, adf4113 = 900 mhz. 6 the synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the vco, pn tot , and subtracting 20logn (where n is the n divider value) and 10logf pfd : pn synth = pn tot C 10logf pfd C 20logn. 7 the phase noise is measured with the eval-adf411x eb1 evaluation board and the hp8562e spec trum analyzer. the spectrum analyzer provides the refin for the synthesizer (f refout = 10 mhz @ 0 dbm). sync = 0; dly = 0 (ta ). ble 7 8 f refin = 10 mhz; f pfd = 200 khz; offset frequency = 1 khz; f rf = 540 mhz; n = 2700; loop b/w = 20 khz. 9 f refin = 10 mhz; f pfd = 200 khz; offset frequency = 1 khz; f rf = 900 mhz; n = 4500; loop b/w = 20 khz. 10 f refin = 10 mhz; f pfd = 30 khz; offset frequency = 300 hz; f rf = 836 mhz; n = 27867; loop b/w = 3 khz. 11 f refin = 10 mhz; f pfd = 200 khz; offset frequency = 1 khz; f rf = 1750 mhz; n = 8750; loop b/w = 20 khz 12 f refin = 10 mhz; f pfd = 10 khz; offset frequency = 200 hz; f rf = 1750 mhz; n = 175000; loop b/w = 1 khz. 13 f refin = 10 mhz; f pfd = 200 khz; offset frequency = 1 khz; f rf = 1960 mhz; n = 9800; loop b/w = 20 khz. 14 f refin = 10 mhz; f pfd = 1 mhz; offset frequency = 1 khz; f rf = 3100 mhz; n = 3100; loop b/w = 20 khz.
adf4110/adf4111/a df4112/adf4113 r e v. c | pa ge 5 o f 2 8 timing characteristics g u a r an t e e d b y desig n b u t n o t pr o d uc t i o n t e st e d . a v dd = d v dd = 3 v 10%, 5 v 10%; a v dd v p 6 v ; a g nd = d g nd = cpgnd = 0 v ; r set = 4.7 k?; t a = t min to t max , u n l e ss ot he r w i s e note d. t a bl e 2. parameter limit at t min to t ma x (b version ) unit test condition s /comments t 1 10 ns min data to clock setup time t 2 10 ns min data to clock hold time t 3 25 ns min clock high duration t 4 25 ns min clock low d u ra tion t 5 10 ns min clock to le setup time t 6 20 ns min le pulse width cloc k data le le db20 (msb) db19 db2 db1 (control bit c2) db0 (lsb) (control bit c1) t 1 t 2 t 3 t 4 t 5 t 6 03496-0-002 f i g u re 2. ti ming d i ag r a m
adf4110/adf4111/a df4112/adf4113 r e v. c | pa ge 6 o f 2 8 absolute maximum ra tings t a = 25c, unles s o t h e r w is e n o ted t a bl e 3. p a r a m e t e r r a t i n g av dd to gnd 1 ?0.3 v to +7 v av dd to dv dd ?0.3 v to +0.3 v v p to gnd ?0.3 v to +7 v v p to av dd ?0.3 v to +5.5 v digital i/o voltage to gnd ?0.3 v to v dd + 0.3 v analog i/o voltage to gnd ?0.3 v to v p + 0. 3 v ref in , rf in a, rf in b to gnd ?0.3 v to v dd + 0.3 v rf in a to rf in b 3 2 0 m v operating tem p erature range indus t rial (b vers io n) ?40c to +85c storage temperature range ?65c to +150c maximum junction temperature 150c tssop ja ther mal impedance 150.4c/w lfcsp ja ther mal imp e dance (paddl e sol d ered) 122c/w lfcsp ja ther mal imp e dance (paddl e not sol d ered) 216c/w lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c 1 gnd = agnd = dgnd = 0 v. s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s ra t i n g onl y ; f u n c t i o n al o p era t ion o f t h e de vice a t t h es e o r an y o t h e r con d i t io ns a b o v e t h os e list e d i n t h e o p era t io nal s e c t io n s o f t h is sp e c if ic a t io n is n o t i m pli e d . e x p o sur e t o a b s o l u t e max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . this de vice is a hig h p e r f o r ma n c e rf in t e g r a t e d cir c ui t wi t h an e s d r a t i ng of < 2 k v , a n d it i s e s d s e ns it ive. pr op e r pre c aut i on s s h o u ld b e ta k e n f o r ha n d lin g and as s e m b l y . tr ansist or c o unt 6425 (cm o s) a nd 303 (b i p ola r ). esd c a ution esd (electrostatic discharge) sensitive device. ele c trosta tic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge with out detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
adf4110/adf4111/a df4112/adf4113 rev. c | page 7 of 28 pin configurations and function descriptions 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 dv dd muxout le v p data clk ce dgnd r set cp c pgnd agnd rf in b rf in a av dd ref in top view (not to scale) adf4110 adf4111 adf4112 adf4113 03496-0-003 1 2 3 4 5 15 16 17 18 19 20 14 13 12 11 6 7 9 10 8 cpgnd agnd agnd rf in b rf in a muxout le data clk ce cp r set v p dv d d dv d d av dd av dd ref in dgnd dgnd top view (not to scale) adf4110 adf4111 adf4112 adf4113 03496-0-004 figure 3. tssop pin configuration figure 4. lfcsp pin configuration table 4. pin function descriptions tssop pin no. lfcsp pin no. mnemonic function 1 19 r set connecting a resistor between this pin and cpgnd sets the maximum charge pump output current. the nominal voltage potential at the r set pin is 0.56 v. the relationship between i cp and r set is set max cp r i 5 . 23 = so, with r set = 4.7 k?, i cpmax = 5 ma. 2 20 cp charge pump output. when enabled, this provides i cp to the external loop filter, which in turn drives the external vco. 3 1 cpgnd charge pump ground. this is the ground return path for the charge pump. 4 2, 3 agnd analog ground. this is the ground return path of the prescaler. 5 4 rf in b complementary input to the rf pres caler. this point should be deco upled to the ground plane with a small bypass capacitor, typically 100 pf. see figure 29. 6 5 rf in a input to the rf prescaler. this small-signal input is ac-coupled from the vco. 7 6, 7 av dd analog power supply. this may range from 2.7 v to 5.5 v. decoupling capa citors to the analog ground plane should be placed as close as possible to this pin. av dd must be the same value as dv dd . 8 8 ref in reference input. this is a cmos in put with a nominal threshold of v dd /2, and an equivalent input resistance of 100 k?. see figure 28. this input can be driven from a ttl or cmos crystal oscillator, or can be ac-coupled. 9 9, 10 dgnd digital ground. 10 11 ce chip enable. a logic low on this pin powers down the device and puts the charge pump output into three-state mode. taking the pin high powers up th e device depending on the status of the power- down bit f2. 11 12 clk serial clock input. this serial cloc k is used to clock in the serial da ta to the registers. the data is latched into the 24-bit shift register on the clk ri sing edge. this input is a high impedance cmos input. 12 13 data serial data input. the serial data is loaded msb first with the two lsbs be ing the control bits. this input is a high impedance cmos input. 13 14 le load enable, cmos input. when le goes high, the data stored in th e shift registers is loaded into one of the four latches; the latch is selected using the control bits. 14 15 muxout this multiplexer output allows either the lock de tect, the scaled rf, or the scaled reference frequency to be accessed externally. 15 16, 17 dv dd digital power supply. this may range from 2.7 v to 5.5 v. decoupling capa citors to the digital ground plane should be placed as close as possible to this pin. dv dd must be the same value as av dd . 16 18 v p charge pump power supply. this shou ld be greater than or equal to v dd . in systems where v dd is 3 v, v p can be set to 6 v and used to drive a vco with a tuning range of up to 6 v.
adf4110/adf4111/a df4112/adf4113 r e v. c | pa ge 8 o f 2 8 typical perf orm ance cha r acte ristics freq param data keyword impedance ?unit ?type ?format ?ohms ghz s m a r 50 freq mags11 angs11 1.05 0.9512 ?40.134 1.10 0.93458 ?43.747 1.15 0.94782 ?44.393 1.20 0.96875 ?46.937 1.25 0.92216 ?49.6 1.30 0.93755 ?51.884 1.35 0.96178 ?51.21 1.40 0.94354 ?53.55 1.45 0.95189 ?56.786 1.50 0.97647 ?58.781 1.55 0.98619 ?60.545 1.60 0.95459 ?61.43 1.65 0.97945 ?61.241 1.70 0.98864 ?64.051 1.75 0.97399 ?66.19 1.80 0.97216 ?63.775 freq mags11 angs11 0.05 0.89207 ?2.0571 0.10 0.8886 ?4.4427 0.15 0.89022 ?6.3212 0.20 0.96323 ?2.1393 0.25 0.90566 ?12.13 0.30 0.90307 ?13.52 0.35 0.89318 ?15.746 0.40 0.89806 ?18.056 0.45 0.89565 ?19.693 0.50 0.88538 ?22.246 0.55 0.89699 ?24.336 0.60 0.89927 ?25.948 0.65 0.87797 ?28.457 0.70 0.90765 ?29.735 0.75 0.88526 ?31.879 0.80 0.81267 ?32.681 0.85 0.90357 ?31.522 0.90 0.92954 ?34.222 0.95 0.92087 ?36.961 1.00 0.93788 ?39.343 03496-0-005 f i gure 5. s- p a r a m e ter d a ta fo r the a d f41 1 3 r f input (up to 1.8 gh z) ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 rf inp u t p o we r (dbm) 0 123 4 5 rf input frequency (ghz) 03496-0-006 v dd = 3v v p = 3v t a = +85 c t a = +25c t a = ? 40c f i g u re 6. input s e n s it iv it y (a df4 1 13) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 outp ut p o w e r (db) ? 2.0khz ? 1.0khz 900mhz 1.0khz 2.0khz frequency 03496-0-007 v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 200khz loop bandwidth = 20khz res. bandwidth = 10hz video bandwidth = 10hz sweep = 1.9 s averages = 19 reference level = ? 4.2dbm ?91.0dbc/hz f i g u re 7 a d f4 1 13 phas e n o is e (9 0 0 m h z, 20 0 k h z, 2 0 k h z ) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 outp ut p o w e r (db) ?2.0khz ?1.0khz 900mhz 1.0khz 2.0khz frequency 03496-0-008 v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 200khz loop bandwidth = 20khz res. bandwidth = 10hz video bandwidth = 10hz sweep = 1.9 s averages = 19 reference level = ? 4.2dbm ?92.5dbc/hz f i gur e 8 . adf4 11 3 p h a s e no i s e (90 0 mh z, 20 0kh z , 20 k h z) w i th dl y a n d sync e n ab led ?140 ?130 ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 p has e nois e (dbc /hz) frequency offset from 900mhz carrier (hz) 1k 100 10k 100k 1m 03496-0-009 rms noise = 0.52 r l = ? 40dbc/hz f i g u re 9. a d f 4 1 1 3 i n teg r ated phas e n o is e (90 0 mh z, 20 0 k h z, 20 kh z, t y pic a l l o c k t i me: 4 0 0 s) ?140 ?130 ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ph a se n o ise ( d b c /h z) frequency offset from 900mhz carrier (hz) 1k 100 10k 100k 1m 03496-0-010 rms noise = 0.62 r l = ? 40dbc/hz f i g u re 10. a d f4 11 3 int e g r ated phas e nois e (90 0 mh z, 20 0 k h z, 35 kh z, t y pic a l l o c k t i me: 2 0 0 s)
adf4110/adf4111/a df4112/adf4113 r e v. c | pa ge 9 o f 2 8 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 outp ut p o w e r (db) ?400khz ?200khz 900mhz 200khz 400khz frequency 03496-0-0 1 1 v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 200khz loop bandwidth = 20khz res. bandwidth = 1khz video bandwidth = 1khz sweep = 2.5s averages = 30 reference level = ? 4.2dbm ?90.2dbc/hz f i g u re 11. a d f4 11 3 r e f e r e nce spu r s ( 9 0 0 m h z, 20 0 k h z, 20 k h z) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 outp ut p o w e r (db) ? 400khz ? 200khz 900mhz 200khz 400khz frequency 03496-0-012 v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 200khz loop bandwidth = 35khz res. bandwidth = 1khz video bandwidth = 1khz sweep = 2.5s averages = 30 reference level = ? 4.2dbm ?89.3dbc/hz f i g u re 12. a d f4 11 3 (9 0 0 m h z, 20 0 k h z, 3 5 k h z) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 outp ut p o w e r (db) ? 400hz ?200hz 1750mhz 200hz 400hz frequency 03496-0-013 v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 30khz loop bandwidth = 3khz res. bandwidth = 10khz video bandwidth = 10khz sweep = 477ms averages = 10 reference level = ? 8.0dbm ?75.2dbc/hz f i g u re 13. a d f4 11 3 p h as e n o is e (1 75 0 m h z, 30 k h z, 3 k h z) ?140 ?130 ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ph a se n o ise ( d b c /h z) frequency offset from 1750mhz carrier (hz) 1k 100 10k 100k 1m 03496-0-014 rms noise = 1.6 r l = ? 40dbc/hz f i g u re 14. a d f4 11 3 int e g r ated phas e nois e (17 5 0 mh z, 3 0 k h z, 3 kh z) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 outp ut p o w e r (db) ?80khz ?40khz 1750mhz 40khz 80khz frequency 03496-0-015 v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 30khz loop bandwidth = 3khz res. bandwidth = 3hz video bandwidth = 3hz sweep = 255s positive peek detect mode reference level = ? 5.7dbm ?79.6dbc/hz f i g u re 15. a d f4 11 3 r e f e r e nce spu r s ( 1 7 5 0 m h z , 3 0 k h z, 3 k h z) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 outp ut p o w e r (db) ?2.0khz ?1.0khz 3100mhz 1.0khz 2.0khz frequency 03496-0-016 v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 1mhz loop bandwidth = 100khz res. bandwidth = 10hz video bandwidth = 10hz sweep = 1.9s averages = 45 reference level = ? 4.2dbm ?86.6dbc/hz f i g u re 16. a d f4 11 3 p h as e n o is e (3 10 0 m h z, 1 m h z, 10 0 k h z)
adf4110/adf4111/a df4112/adf4113 rev. c | page 10 of 28 ?140 ?130 ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ph a se n o ise ( d b c /h z) frequency offset from 3100mhz carrier (hz) 10 3 10 2 10 4 10 5 10 6 03496-0-017 rms noise = 1.7 r l = 40dbc/hz f i g u re 17. a d f4 11 3 int e g r ated phas e nois e (3 10 0 mhz , 1 mhz, 1 0 0 kh z ) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 outp ut p o w e r (db) ? 2.0mhz ?1.0mhz 3100mhz 1.0mhz 2.0mhz frequency 03496-0-018 v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 1mhz loop bandwidth = 100khz res. bandwidth = 1khz video bandwidth = 1khz sweep = 13s averages = 1 reference level = ? 17.2dbm ?80.6dbc/hz f i g u re 18. r e f e rence spurs ( 3 1 0 0 m h z, 1 m h z, 1 00 k h z) ?180 ?170 ?160 ?150 ?140 ?130 ?120 ph a se n o ise ( d b c /h z) phase detec t or frequency (khz) 10 1 100 1000 10000 03496-0-019 v dd = 3v v p = 5v f i g u re 19. a d f4 11 3 p h as e n o is e (r ef e r r e d to cp o u t p ut ) vs . p h a s e d e t e c t or f r e q ue nc y ph a se n o ise ( d b c /h z) ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?40 ? 20 0 2 0 4 0 6 0 8 0 100 tempera ture (c) 03496-0-020 v dd = 3v v p = 3v f i g u re 20. a d f4 11 3 p h as e n o is e v s . t e mper at ur e (90 0 mh z, 20 0 k h z, 20 kh z) firs t re fe re nce s p ur (dbc ) ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?40 ? 20 0 2 0 4 0 6 0 8 0 100 tempera ture (c) 03496-0-021 v dd = 3v v p = 5v f i g u re 21. a d f4 11 3 r e f e r e nce spu r s v s . t e mper at ure (90 0 mh z, 20 0 k h z, 20 kh z) ?105 ?95 ?85 ?75 ?65 ?55 ?45 ?35 ?25 ?15 ?5 first reference spur (dbc ) 0 123 4 5 tuning volt age (v ) 03496-0-022 v dd = 3v v p = 5v f i g u re 22. a d f4 11 3 r e f e r e nce spu r s ( 2 0 0 k h z) v s . v tu ne (90 0 mh z, 20 0 k h z, 20 kh z)
adf4110/adf4111/a df4112/adf4113 rev. c | page 11 of 28 ph a se n o ise ( d b c /h z) ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?40 ? 20 0 2 0 4 0 6 0 8 0 100 tempera ture (c) 03496-0-023 v dd = 3v v p = 5v f i g u re 23. a d f4 11 3 p h as e n o is e v s . t e mper at ur e (83 6 mh z, 30 kh z, 3 kh z) firs t re fe re nce s p ur (dbc ) ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?40 ? 20 0 2 0 4 0 6 0 8 0 100 tempera ture (c) 03496-0-024 v dd = 3v v p = 5v f i g u re 24. a d f4 11 3 r e f e r e nce spu r s v s . t e mper at ure (83 6 mh z, 30 kh z, 3 kh z) 0 1 2 3 4 5 6 7 8 9 10 ai dd (ma) prescaler v alu e 8/9 0 16/17 32/33 64/65 03496-0-025 adf4113 adf4112 adf4110 adf4111 f i g u re 25. a i dd v s . p r esc a l e r v a lu e 0 0.5 1.0 1.5 2.0 2.5 3.0 di dd (ma) prescaler output frequenc y (mhz ) 50 0 100 150 200 03496-0-026 v dd = 3v v p = 3v f i g u re 26. di dd vs. pr esc a ler o u tput f r e q uenc y (a df41 10, a d f4 11 1, a d f 4 1 12, a d f4 1 13) ?6 ?4 ?2 ?3 ?5 0 ?1 i cp (ma) 2 1 4 3 6 5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 v cp (v) 03496-0-027 v pp = 5v i cp = 5ma f i g u re 27. cha r g e p u mp o u t p ut ch ar a c ter i s t ics f o r a d f 4 1 10 f a m ily
adf4110/adf4111/a df4112/adf4113 rev. c | page 12 of 28 circuit description reference input section the reference input stage is shown in figure 28. sw1 and sw2 are normally closed switches. sw3 is normally open. when power-down is initiated, sw3 is closed and sw1 and sw2 are opened. this ensures that there is no loading of the ref in pin on power-down. buffer to r counter ref in 100k ? nc sw2 sw3 no nc sw1 power-down control 03496-0-028 figure 28. reference input stage rf input stage the rf input stage is shown in figure 29. it is followed by a two-stage limiting amplifier to generate the current mode logic (cml) clock levels needed for the prescaler. av dd agnd 500 ? 500 ? 1.6v bias generator rf in a rf in b 03496-0-029 figure 29. rf input stage prescaler (p/p + 1) along with the a and b counters, the dual-modulus prescaler (p/p + 1) enables the large division ratio, n, to be realized (n = bp + a). the dual-modulus prescaler, operating at cml levels, takes the clock from the rf input stage and divides it down to a manageable frequency for the cmos a and b counters. the prescaler is programmable; it can be set in software to 8/9, 16/17, 32/33, or 64/65. it is based on a synchronous 4/5 core. a and b counters the a and b cmos counters combine with the dual-modulus prescaler to allow a wide ranging division ratio in the pll feedback counter. the counters are specified to work when the prescaler output is 200 mhz or less. thus, with an rf input frequency of 2.5 ghz, a prescaler value of 16/17 is valid but a value of 8/9 is not. pulse swallow function the a and b counters, in conjunction with the dual-modulus prescaler, make it possible to generate output frequencies that are spaced only by the reference frequency divided by r . the equation for the vco frequency is f vco = [( p b ) + a ] f refin / r where: f vco = output frequency of external voltage controlled oscillator (vco) p = preset modulus of dual-modulus prescaler b = preset divide ratio of binary 13-bit counter(3 to 8191) a = preset divide ratio of binary 6-bit swallow counter (0 to 63) f refin = output frequency of the external reference frequency oscillator r = preset divide ratio of binary 14-bit programmable reference counter (1 to 16383) r counter the 14-bit r counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (pfd). division ratios from 1 to 16,383 are allowed. 13-bit b counter 6-bit a counter prescaler p/p + 1 from rf input stage modulus control n = bp + a load load to pfd 03496-0-030 figure 30. a and b counters
adf4110/adf4111/a df4112/adf4113 rev. c | page 13 of 28 lo c k d e t e c t phase frequency de t e c t or (p fd ) an d charge pu mp mux o ut can be p r ogra mm e d f o r tw o typ e s o f lo c k d e t e ct: dig i t a l lo ck de te c t a nd a n a l o g lo ck dete c t . the p f d t a k e s i n p u ts f r o m t h e r co un t e r and n co un t e r (n = bp + a ) a n d pro d u c e s a n output prop or t i on a l to t h e ph a s e a n d f r e q uen c y dif f er en c e b e tw e e n t h em. f i gur e 31 is a sim p lif i e d s c h e ma t i c. th e p f d i n cl udes a p r og ra mma b l e de l a y e l e m e n t tha t con t r o ls the wid t h o f t h e an tibacklas h p u ls e . this p u ls e en s u r e s t h a t t h e r e is n o de ad zon e i n t h e p f d t r a n sfer f u n c t i o n a nd mi nim i zes phas e n o is e and r e fer e n c e sp urs. t w o b i t s in t h e re f e re nc e c o u n t e r l a tc h , a b p 2 a n d a b p 1 , c o n t r o l t h e w i d t h of t h e p u ls e . s e e t a b l e 7. d i gi tal lock d e t e ct i s a c ti v e hi g h . w h e n l d p i n th e r co un t e r la t c h is s e t t o 0, dig i t a l lo c k det e c t is s e t hig h w h en t h e p has e er r o r o n t h r e e co n s e c u t i v e phas e det e c t o r (pd) c y cles is les s tha n 15 n s . w i t h ld p s e t t o 1, f i v e co n s ec u t i v e c y c l es o f les s tha n 15 n s a r e req u ir ed t o s e t t h e lo ck detec t . i t s t a y s hig h u n ti l a phas e er r o r g r e a t e r t h an 25 n s is det e c t e d on an y sub s e q ue n t pd c y cl e. the n-c h a n ne l o p en-dra in a n al og lo c k det e c t sh o u ld be o p era t e d wi t h a 10 k? n o minal ext e r n al p u l l -u p r e sis t o r . w h en lo c k has been det e c t e d , this o u t p u t is hig h wi t h na r r o w l o w- going p u l s e s . p programmable delay u3 clr2 q2 d2 u2 clr1 q1 d1 charge pump down up hi hi u1 abp1 abp2 r divider n divider cp output r divider n divider cp cpgnd v 03496- 0- 031 control mux dv dd muxout dgnd a nalog lock detec t digital lock detect r counter output n counter output sdout 03496- 0- 032 f i g u re 32. m u x o u t ci r c u i t inpu t shift register the ad f4110 f a mil y dig i tal s e c t io n in c l udes a 24-b i t in p u t s h if t r e g i s t er , a 14-b i t r co un t e r , an d a 19-b i t n co un t e r co m p r i s e d o f a 6-b i t a co u n t e r a n d a 13-b i t b co un t e r . da ta is c l o c k e d in t o the 24-b i t sh if t r e g i st er o n e a ch r i sin g e d ge o f cl k ms b f i rst. d a t a is t r a n sfer r e d f r o m t h e s h if t r e g i s t er t o o n e o f fo ur la t c h e s on t h e r i sin g e d ge o f le. th e de s t ina t ion l a t c h is det e r m i n e d b y t h e s t a t e o f t h e tw o co n t r o l b i ts (c2, c1) in t h e s h if t r e g i s t er . th e s e a r e th e tw o ls b s , d b 1 a nd d b 0, as s h own in f i gur e 2. th e tr u t h t a b l e fo r t h es e b i ts is sh o w n i n t a b l e 5. f i gur e 3 1 . p f d simpl i f ie d s c hema ti c and t i mi ng (in l o c k ) mux o ut a n d l o c k de tec t the o u t p u t m u l t i p lexer o n th e ad f4110 fa mily al lo ws th e us er t o acces s va r i o u s in t e r n al p o in ts o n t h e chi p . the s t a t e o f mux o ut is co n t r o l l ed b y m3, m2, a nd m1 in t h e f u n c tio n la t c h . t a b l e 9 sh o w s th e full tr u t h ta b l e . f i gur e 32 s h o w s t h e mu x o u t s e c t i o n in b l o c k di a g r a m fo r m . t a b l e 6 sh o w s a s u mma r y o f h o w the la t c h e s a r e p r og ra mm e d . t a bl e 5. c2, c1 t r u t h t a bl e control bits c 2 c 1 d a t a l a t c h 0 0 r counter 0 1 n counter (a an d b) 1 0 function latch (including prescaler) 1 1 initialization latch
adf4110/adf4111/a df4112/adf4113 rev. c | page 14 of 28 t a bl e 6. ad f41 10 f a mi l y l a t c h s u m m ar y n counter latch db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db13 b13 b12 b11 b8 b7 b6 b5 b4 b2 b1 a6 a5 a4 a3 a2 a1 c2 (0) c1 (1) b3 13-bit b counter control bits reserved db2 db1 db0 g1 b10 b9 6-bit a counter n i a g p c function latch db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db13 cpi6 cpi5 cpi4 cpi1 tc4 tc3 tc2 tc1 f4 f3 f2 m3 m2 m1 pd1 f1 c2 (1) c1 (0) f5 timer counter control control bits prescaler value db2 db1 db0 pd2 cpi3 cpi2 - r e w o p 2 n w o d muxout control current setting 1 current setting 2 k c o l t s a f e d o m k c o l t s a f e l b a n e p c - e e r h t e t a t s d p y t i r a l o p - r e w o p 1 n w o d r e t n u o c t e s e r p1 p2 initialization latch db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db13 cpi6 cpi5 cpi4 cpi1 tc4 tc3 tc2 tc1 f4 f3 f2 m3 m2 m1 pd1 f1 c2 (1) c1 (1) f5 timer counter control control bits prescaler value db2 db1 db0 pd2 cpi3 cpi2 - r e w o p 2 n w o d muxout control current setting 1 current setting 2 k c o l t s a f e d o m k c o l t s a f e l b a n e p c e t a t s - e e r h t d p y t i r a l o p - r e w o p 1 n w o d r e t n u o c t e s e r p1 p2 test mode bits db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db13 ldp t2 t1 r14 r13 r12 r11 r10 r8 r7 r6 r5 r4 r3 r2 r1 c2 (0) c1 (0) r9 14-bit reference counter, r control bits d e v r e s e r db2 db1 db0 sync dly abp2 abp1 anti- backlash width sync dly k c o l t c e t e d n o i s i c e r p reference counter latch x xx x = don't care x = don't care 03496-0-033
adf4110/adf4111/a df4112/adf4113 rev. c | page 15 of 28 t a b l e 7 . re fere n c e c o u n ter l a tc h map operation ldp three consecutive cycles of phase delay less than 15ns must occur before lock detect is set. five consecutive cycles of phase delay less than 15ns must occur before lock detect is set. 0 1 test mode bits should be set to 00 for normal operation r14 0 0 0 0 ? ? ? 1 1 1 1 r13 0 0 0 0 ? ? ? 1 1 1 1 r12 0 0 0 0 ? ? ? 1 1 1 1 r3 0 0 0 1 ? ? ? 1 1 1 1 r2 0 1 1 0 ? ? ? 0 0 1 1 r1 1 0 1 0 ? ? ? 0 1 0 1 divide ratio 1 2 3 4 ? ? ? 16380 16381 16382 16383 ??? ??? ???? ?? ???? ??? ? ?? ???? ??? ? ?? ???? ??? ? ?? ???? ??? ? ?? ???? ??? ? ?? ???? ??? ? ?? ???? ??? ? ?? ???? ??? ? ?? ???? ??? ? ?? ???? ??? ? ??? ??? ??? ? test mode bits db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db13 ldp t2 t1 r14 r13 r12 r11 r10 r8 r7 r6 r5 r4 r3 r2 r1 c2 (0) c1 (0) r9 14-bit reference counter control bits d e v r e s e r db2 db1 db0 sync dly abp2 abp1 anti- backlash width sync dly k c o l t c e t e d n o i s i c e r p abp1 abp2 0 0 1 1 0 1 0 1 3.0ns 1.5ns 6.0ns 3.0ns antibacklash pulse width sync dly 0 0 1 1 0 1 0 1 normal operation output of prescaler is resynchronized with nondelayed version of rf input normal operation output of prescaler is resynchronized with delayed version of rf input operation x x = don't care 03496-0-034
adf4110/adf4111/a df4112/adf4113 rev. c | page 16 of 28 t a b l e 8 . a b c o u n ter l a tc h ma p these bits are not used by the device and are don't care bits a6 0 0 0 0 ? ? ? 1 1 1 1 a5 0 0 0 0 ? ? ? 1 1 1 1 a2 0 0 1 1 ? ? ? 0 0 1 1 a1 0 1 0 1 ? ? ? 0 1 0 1 a counter divide ratio 0 1 2 3 ? ? ? 60 61 62 63 ??? ???? ?? ? ??? ???? ?? ? ??? ???? ?? ? ??? ???? ?? ? ??? ???? ?? ? ??? ???? ?? ? ???? ??? ?? ? ???? ??? ?? ? ???? ??? ?? ? ???? ??? ?? ? ???? ??? ?? ? ???? ??? ?? ? b13 0 0 0 0 0 ? ? ? 1 1 1 1 b12 0 0 0 0 0 ? ? ? 1 1 1 1 b11 0 0 0 0 0 ? ? ? 1 1 1 1 b3 b2 b1 b counter divide ratio ?? ???? ??? ? ??? ???? ?? ? ??? ???? ?? ? ??? ???? ?? ? ??? ???? ?? ? ??? ???? ?? ? ??? ???? ?? ? ??? ???? ?? ? ??? ???? ?? ? ??? ???? ?? ? ??? ???? ?? ? ???? ??? ?? ? ???? ??? ?? ? 0 0 0 0 1 ? ? ? 1 1 1 1 0 0 1 1 0 ? ? ? 0 0 1 1 0 1 0 1 0 ? ? ? 0 1 0 1 not allowed not allowed not allowed 3 4 ? ? ? 8188 8189 8190 8191 13-bit b counter db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db13 b13 b12 b11 b8 b7 b6 b5 b4 b2 b1 a6 a5 a4 a3 a2 a1 b3 6-bit a counter reserved db2 g1 b10 b9 n i a g p c *see table 9 f4 (function latch) fastlock enable* cp gain operation 0 0 1 1 0 1 0 1 charge pump current setting 1 is permanently used. charge pump current setting 2 is permanently used. charge pump current setting 1 is used. charge pump current is switched to setting 2. the time spent in setting 2 is dependent upon which fastlock mode is used. see function latch description. n = bp + a, p is prescaler value set in the function latch, b must be greater than or equal to a. for continuously adjacent values of (n x f ref ), at the output, n min is (p 2 ? p). x x = don't care x c2 (0) c1 (1) control bits db1 db0 03496-0-035
adf4110/adf4111/a df4112/adf4113 rev. c | page 17 of 28 t a bl e 9. f u nc ti o n l a t c h m a p m3 0 0 0 0 1 1 1 1 m2 0 0 1 1 0 0 1 1 m1 0 1 0 1 0 1 0 1 output three-state output digital lock detect (active high) n divider output dv dd r divider output analog lock detect (n-channel open-drain) serial data output dgnd f1 0 1 counter operation normal r, a, b counters held in reset f2 0 1 phase detector polarity negative positive f3 0 1 charge pump output normal three-state 0 1 1 1 ce pin pd2 pd1 mode asynchronous power-down normal operation asynchronous power-down synchronous power-down x x 0 1 x 0 1 1 f5 x 0 1 fastlock mode fastlock disabled fastlock mode 1 fastlock mode 2 f4 0 1 1 p1 0 1 0 1 prescaler value 8/9 16/17 32/33 64/65 p2 0 0 1 1 cpi6 cpi3 cpi5 cpi2 cpi4 cpi1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 i cp (ma) 2.7k ? 4.7k ? 10k ? 1.09 2.18 3.26 4.35 5.44 6.53 7.62 8.70 0.63 1.25 1.88 2.50 3.13 3.75 4.38 5.00 0.29 0.59 0.88 1.76 1.47 1.76 2.06 2.35 current setting 2 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db13 cpi6 cpi5 cpi4 cpi1 tc4 tc3 tc2 tc1 f4 f3 f2 m3 m2 m1 pd1 f1 c2(1) c1(0) f5 control bits prescaler value db2 db1 db0 pd2 p1 cpi3 cpi2 - r e w o p 2 n w o d current setting 1 timer counter control k c o l t s a f e d o m k c o l t s a f e l b a n e p c e t a t s - e e r h t d p y t i r a l o p muxout control - r e w o p 1 n w o d r e t n u o c t e s e r p2 tc4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 tc3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 tc2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 tc1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 timeout (pfd cycles) 3 7 11 15 19 23 27 31 35 39 43 47 51 55 59 63 see function latch, timer counter control section 03496-0-036
adf4110/adf4111/a df4112/adf4113 rev. c | page 18 of 28 t a bl e 10. i n iti a liza ti o n l a t c h m a p m3 0 0 0 0 1 1 1 1 m2 0 0 1 1 0 0 1 1 m1 0 1 0 1 0 1 0 1 output three-state output digital lock detect (active high) n divider output dv dd r divider output analog lock detect (n-channel open-drain) serial data output dgnd tc4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 tc3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 tc2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 tc1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 timeout (pfd cycles) 3 7 11 15 19 23 27 31 35 39 43 47 51 55 59 63 f1 0 1 counter operation normal r, a, b counters held in reset f2 0 1 phase detector polarity negative positive f3 0 1 charge pump output normal three-state 0 1 1 1 ce pin pd2 pd1 mode asynchronous power-down normal operation asynchronous power-down synchronous power-down x x 0 1 x 0 1 1 f5 x 0 1 fastlock mode fastlock disabled fastlock mode 1 fastlock mode 2 f4 0 1 1 p1 0 1 0 1 prescaler value 8/9 16/17 32/33 64/65 p2 0 0 1 1 cpi6 cpi3 cpi5 cpi2 cpi4 cpi1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 i cp (ma) 2.7k ? 4.7k ? 10k ? 1.09 2.18 3.27 4.35 5.44 6.53 7.62 8.70 0.63 1.25 1.88 2.50 3.13 3.75 4.38 5.00 0.29 0.59 0.88 1.76 1.47 1.76 2.06 2.35 current setting 2 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db13 cpi6 cpi5 cpi4 cpi1 tc4 tc3 tc2 tc1 f4 f3 f2 m3 m2 m1 pd1 f1 c2 (1) c1 (1) f5 control bits prescaler value db2 db1 db0 pd2 p1 cpi3 cpi2 - r e w o p 2 n w o d current setting 1 timer counter control k c o l t s a f e d o m k c o l t s a f e l b a n e p c e t a t s - e e r h t d p y t i r a l o p muxout control - r e w o p 1 n w o d r e t n u o c t e s e r p2 see function latch, timer counter control section 03496-0-037
adf4110/adf4111/a df4112/adf4113 rev. c | page 19 of 28 function latch the on-chip function latch is programmed with c2, c1 set to 1. table 9 shows the input data format for programming the function latch. counter reset db2 (f1) is the counter reset bit. when db2 is 1, the r counter and the ab counters are reset. for normal operation, this bit should be 0. upon powering up, the f1 bit must be disabled, and the n counter resumes counting in close alignment with the r counter. (the maximum error is one prescaler cycle.) power-down db3 (pd1) and db21 (pd2) on the adf411x provide program- mable power-down modes. they are enabled by the ce pin. when the ce pin is low, the device is immediately disabled regardless of the states of pd2, pd1. in the programmed asynchronous power-down, the device powers down immediately after latching a 1 into bit pd1, provided pd2 has been loaded with a 0. in the programmed synchronous power-down, the device power-down is gated by the charge pump to prevent unwanted frequency jumps. once power-down is enabled by writing a 1 into bit pd1 (provided a 1 has also been loaded to pd2), the device goes into power-down on the next charge pump event. when a power-down is activated (either synchronous or asynchronous mode including ce pin activated power-down), the following events occur: ? all active dc current paths are removed. ? the r, n, and timeout counters are forced to their load state conditions. ? the charge pump is forced into three-state mode. ? the digital clock detect circuitry is reset. ? the rfin input is debiased. ? the reference input buffer circuitry is disabled. ? the input register remains active and capable of loading and latching data. muxout control the on-chip multiplexer is controlled by m3, m2, and m1 on the adf4110 family. table 9 shows the truth table. fastlock enable bit db9 of the function latch is the fastlock enable bit. fastlock is enables only when this is 1. fastlock mode bit db10 of the function latch is the fastlock enable bit. when fastlock is enabled, this bit determines which fastlock mode is used. if the fastlock mode bit is 0, fastlock mode 1 is selected; if the fastlock mode bit is 1, fastlock mode 2 is selected. fastlock mode 1 the charge pump current is switched to the contents of current setting 2. the device enters fastlock by having a 1 written to the cp gain bit in the ab counter latch. the device exits fastlock by having a 0 written to the cp gain bit in the ab counter latch. fastlock mode 2 the charge pump current is switched to the contents of current setting 2. the device enters fastlock by having a 1 written to the cp gain bit in the ab counter latch. the device exits fastlock under the control of the timer counter. after the timeout period determined by the value in tc4 through tc1, the cp gain bit in the ab counter latch is automatically reset to 0 and the device reverts to normal mode instead of fastlock. see table 9 for the timeout periods. timer counter control the user has the option of programming two charge pump cur- rents. current setting 1 is meant to be used when the rf output is stable and the system is in a static state. current setting 2 is meant to be used when the system is dynamic and in a state of change (i.e., when a new output frequency is programmed). the normal sequence of events is as follows: the user initially decides what the preferred charge pump currents are going to be. for example, they may choose 2.5 ma as current setting 1 and 5 ma as current setting 2. at the same time, they must also decide how long they want the secondary current to stay active before reverting to the primary current. this is controlled by the timer counter control bits, db14 through db11 (tc4 through tc1) in the function latch. the truth table is given in table 10. a user can program a new output frequency simply by pro- gramming the ab counter latch with new values for a and b. at the same time, the cp gain bit can be set to 1, which sets the charge pump with the value in cpi6Ccpi4 for a period deter- mined by tc4 through tc1. when this time is up, the charge pump current reverts to the value set by cpi3Ccpi1. at the same time, the cp gain bit in the ab counter latch is reset to 0 and is ready for the next time the user wishes to change the frequency.
adf4110/adf4111/a df4112/adf4113 rev. c | page 20 of 28 note that there is an enable feature on the timer counter. it is enabled when fastlock mode 2 is chosen by setting the fastlock mode bit (db10) in the function latch to 1. charge pump currents cpi3, cpi2, and cpi1 program current setting 1 for the charge pump. cpi6, cpi5, and cpi4 program current setting 2 for the charge pump. the truth table is given in table 10. prescaler value p2 and p1 in the function latch set the prescaler values. the prescaler value should be chosen so that the prescaler output frequency is always less than or equal to 200 mhz. thus, with an rf frequency of 2 ghz, a prescaler value of 16/17 is valid but a value of 8/9 is not. pd polarity this bit sets the phase detector polarity bit. see table 10. cp three-state this bit controls the cp output pin. with the bit set high, the cp output is put into three-state. with the bit set low, the cp output is enabled. initialization latch when c2, c1 = 1, 1, the initialization latch is programmed. this is essentially the same as the function latch (programmed when c2, c1 = 1, 0). however, when the initialization latch is programmed, an addi- tional internal reset pulse is applied to the r and ab counters. this pulse ensures that the ab counter is at load point when the ab counter data is latched, and the device begins counting in close phase alignment. if the latch is programmed for synchronous power-down (ce pin high; pd1 bit high; pd2 bit low), the internal pulse also triggers this power-down. the prescaler reference and the oscillator input buffer are unaffected by the internal reset pulse, so close phase alignment is maintained when counting resumes. when the first ab counter data is latched after initialization, the internal reset pulse is again activated. however, successive ab counter loads after this will not trigger the internal reset pulse. device programming after initial power-up after initial power-up of the device, there are three ways to program the device. initialization latch method apply v dd . program the initialization latch (11 in 2 lsbs of input word). make sure the f1 bit is programmed to 0. then, do an r load (00 in 2 lsbs). then do an ab load (01 in 2 lsbs). when the initialization latch is loaded, the following occurs: 1. the function latch contents are loaded. 2. an internal pulse resets the r, a, b, and timeout counters to load state conditions and three-states the charge pump. note that the prescaler band gap reference and the oscil- lator input buffer are unaffected by the internal reset pulse, allowing close phase alignment when counting resumes. 3. latching the first ab counter data after the initialization word activates the same internal reset pulse. successive ab loads do not trigger the internal reset pulse unless there is another initialization. ce pin method 1. apply v dd . 2. bring ce low to put the device into power-down. this is an asynchronous power-down in that it happens immediately. 3. program the function latch (10). program the r counter latch (00). program the ab counter latch (01). 4. bring ce high to take the device out of power-down. the r and ab counters now resume counting in close alignment. after ce goes high, a duration of 1 s may be required for the prescaler band gap voltage and oscillator input buffer bias to reach steady state. ce can be used to power the device up and down in order to check for channel activity. the input register does not need to be reprogrammed each time the device is disabled and enabled as long as it has been programmed at least once after v dd was initially applied. counter reset method 1. apply v dd . 2. do a function latch load (10 in 2 lsbs). as part of this, load 1 to the f1 bit. this enables the counter reset. 3. do an r counter load (00 in 2 lsbs). do an ab counter load (01 in 2 lsbs). do a function latch load (10 in 2 lsbs). as part of this, load 0 to the f1 bit. this disables the counter reset. this sequence provides the same close alignment as the initiali- zation method. it offers direct control over the internal reset. note that counter reset holds the counters at load point and three states the charge pump but does not trigger synchronous power-down. the counter reset method requires an extra function latch load compared to the initialization latch method.
adf4110/adf4111/a df4112/adf4113 rev. c | page 21 of 28 resynchronizing the prescaler output table 7 (the reference counter latch map) shows two bits, db22 and db21, which are labeled dly and sync, respectively. these bits affect the operation of the prescaler. with sync = 1, the prescaler output is resynchronized with the rf input. this has the effect of reducing jitter due to the prescaler and can lead to an overall improvement in synthesizer phase noise performance. typically, a 1 db to 2 db improvement is seen in the adf4113. the lower bandwidth devices can show an even greater improvement. for example, the adf4110 phase noise is typically improved by 3 db when sync is enabled. with dly = 1, the prescaler output is resynchronized with a delayed version of the rf input. if the sync feature is used on the synthesizer, some care must be taken. at some point, (at certain temperatures and output frequencies), the delay through the prescaler coincides with the active edge on rf input; this causes the sync feature to break down. it is important to be aware of this when using the sync feature. adding a delay to the rf signal, by programming dly = 1, extends the operating frequency and temperature somewhat. using the sync feature also increases the value of the ai dd for the device. with a 900 mhz output, the adf4113 ai dd increases by about 1.3 ma when sync is enabled and by an additional 0.3 ma if dly is enabled. all the typical performance plots in this data sheet, except for figure 8, apply for dly and sync = 0, i.e., no resynchroniza- tion or delay enabled.
adf4110/adf4111/a df4112/adf4113 rev. c | page 22 of 28 appli c a t ions l o c a l oscill a t or for gsm base st a t ion tr ansmit t er f i gur e 33 s h o w s th e ad f4111/ad f4112/ad f 4113 bein g us ed w i th a v c o t o p r od u c e th e l o f o r a g s m b a s e s t a t i o n tra n sm i t t e r . the r e fer e n c e i n p u t sig n al is a pplie d t o t h e cir c ui t a t fref in a n d , in t h i s cas e , is t e r m ina t e d i n 50 ?. a ty p i ca l gs m sy st e m w o u l d ha ve a 13 mh z t c x o dr i v i n g t h e r e fer e n c e in pu t wi t h - o u t an y 50 ? ter m ina t io n. i n o r der to ha ve channel sp aci n g o f 200 kh z (gs m s t anda r d ), the r e f e r e n c e in p u t m u s t be di vide d b y 65, usin g th e o n -c hi p r e f e r e nce divider o f the ad f4111/ ad f4112/ad f 4113. the c h a r g e p u m p o u t p u t o f the ad f4111/adf4112/ad f4113 (p in 2) dr i v es t h e lo o p f i l t er . i n calc u l a t i n g t h e lo o p f i l t er co m p on e n t va l u es, a n u m b er o f i t ems ne e d t o b e co n s ider e d . i n t h is exa m ple , t h e lo o p f i l t er was desig n e d s o t h a t t h e o v eral l p h as e ma rg in fo r th e sys t e m w o u l d be 45 deg r e e s. o t h e r p ll sy st em sp e c if ic a t io n s a r e k d = 5 ma k v = 12 mh z/v l o o p b a nd w i d t h = 20 khz f ref = 200 kh z n = 4500 e x t r a refer e n c e s p ur a t te n u a t i o n = 10 db a l l o f t h es e sp e c if ica t ion s a r e ne e d e d an d us e d t o co m e u p w i t h t h e lo o p f i l t er c o m p on e n t val u e s s h own in f i gu r e 33. the lo o p f i l t er ou t p ut dr i v es t h e v c o , w h ich i n t u r n is fe d b a ck t o t h e rf i n p u t o f t h e p ll syn t h e si zer . i t als o dr i v es t h e rf o u t - p u t t e r m ina l . a t - cir c ui t co nf ig ura t io n p r o v ide s 50 ? ma t c hi ng b e tw e e n t h e v c o o u t p ut, t h e r f o u t p u t , and t h e rf in te r m i n a l of t h e s y n t he s i z e r . i n a pll sy st e m , i t is im p o r t a n t t o k n o w w h en t h e sy st em is in lo ck. i n f i gur e 3 3 , t h is is acco m p lish e d b y usin g t h e m u x o u t sig n al f r o m th e syn t h e sizer . th e mux o ut p i n ca n be p r o- g r a m m e d t o m o ni t o r va r i o u s in ter n al sig n als in th e sy n t h e sizer . on e o f t h es e is t h e l d o r lo ck-det e c t sig n al . adf4111 adf4112 adf4113 ce clk data le 1000pf 1000pf ref in 100pf cp muxout cp gnd agnd dgnd 1nf 8.2nf 620pf 100pf 51 ? 1 3.3k ? 5.6k ? 100pf 18 ? 1 to be used when generator source impedance is 50 ? . 2 optional matching resistor depending on rf out frequency. decoupling capacitors on av dd , dv dd , and v p of the adf411x and on the positive supply of the vco190-902t have been omitted from the diagram to increase clarity. s p i comp atible s e r ial bus r set rf in a rf in b av dd dv dd v p fref in v dd v p lock detect v cc vco190-902t 18 ? 18 ? 100pf rf out 4.7k ? 7 15 16 8 2 14 6 5 1 9 4 3 b c p 51 ? 2 03496-0-038 f i gure 33. l o c a l o s cil l a to r fo r gsm ba s e stati o n
adf4110/adf4111/a df4112/adf4113 rev. c | page 23 of 28 adf4111 adf4112 adf4113 2.7k ? vco gnd 18 ? 100pf 100pf 18 ? 18 ? rf out fref in 51 ? 100pf 100pf rf in a rf in b power supply connections and decoupling capacitors are omitted for clarity. r set ref in cp loop filter ce clk data le spi compatible serial bus ad5320 12-bit v-out dac muxout lock detect input output 2 14 6 5 1 8 03496-0-039 f i g u re 34. d r iv ing t h e r set pin with a d / a c o n v er ter using a d/a c o nverter t o drive the r se t pi n a d/ a con v er t e r ca n b e us e d t o dr i v e t h e r set pi n of t h e ad f4110 fa mily , th us in cr easing th e l e v e l o f con t r o l o v er th e c h a r g e p u m p c u r r en t, i cp . this ca n b e a d van t a g e o us in wi de- b a nd a p plic a t ion s w h er e t h e s e n s i t ivi t y o f t h e v c o va r i es o v er th e t u n i n g ra n g e . t o co m p e n s a t e f o r th i s , th e i cp ma y b e va r i e d t o ma in ta in g o o d p h as e ma rg in a nd ens u r e lo o p s t a b il i t y . s e e f i gur e 34. shutdo w n circuit the a t tached circ ui t in f i gur e 35 s h o w s h o w t o s h u t do wn bo t h th e ad f4110 famil y a nd t h e ac co m p an ying v c o . the ad g7 01 swi t ch g o es c l os ed cir c ui t w h en a l o g i c 1 is a p p l ied t o t h e i n in p u t. th e lo w c o s t swi t ch is a v aila b l e in bo th s o t - 23 an d mso p p a c k a g es. wideb a nd pll m a n y o f th e wire les s a p p l ic a t ion s f o r syn t h e s i zers a nd v c o s in plls a r e na r r o w b a n d in n a t u r e . th e s e a p plic a t io n s i n cl ude t h e va r i o u s wir e les s s t anda r d s li k e gs m, dsc1800, cd ma, an d w c d m a. i n e a ch o f t h es e cas e s, t h e t o t a l t u ni n g ra n g e fo r t h e lo cal os cil l a t o r is les s tha n 100 mh z. h o w e v e r , th er e a r e als o w i d e b a n d ap p l i c at i o n s f o r w h i c h t h e l o c a l o s c i l l a t o r c o u l d h a v e a t u n i n g ra n g e a s wid e as an o c t a ve. f o r exa m ple, ca b l e t v t u n e rs ha v e a t o tal ra n g e o f a b ou t 400 mh z. f i gur e 36 s h o w s an a p p l ic a t ion w h er e th e ad f4113 is us ed t o co n t rol a nd p r og ra m th e m i cr on etics m3500-2235. th e lo o p f i l t er was desig n ed f o r a n rf o u t p u t o f 2900 mh z, a lo o p ba ndwid th of 40 kh z, a p f d fr e q u e n c y o f 1 m h z , i cp o f 10 ma (2.5 ma sy n t h e s i zer i cp m u lt ipl i e d by t h e g a i n f a c t or of 4 ) , v c o k d o f 90 mh z/v (s en si tivi ty o f th e m3500 -2235 a t an o u t p u t o f 2900 mh z), an d a phas e m a rg in o f 45c. i n na r r o w -b an d a p plic a t io ns, t h er e is gen e ra l l y a sma l l va r i a t ion in o u t p u t f r eq u e n c y (g eneral l y les s tha n 10 %) a nd a smal l va r i a t ion i n v c o s e n s i t i v i t y o v er t h e ra n g e ( t y p ical l y 10% t o 15%). h o w e v e r , in wideb a nd a pplica t ion s , b o t h o f t h es e p a ra m e ter s ha ve a m u ch gr ea t e r va r i a t io n . i n f i gur e 36, f o r exa m ple , t h er e is a ?25% and + 17% va r i a t ion i n t h e rf o u t p u t f r o m th e n o minal 2.9 gh z. th e s e n s i t ivi t y o f the v c o can va r y f r o m 120 mh z/v a t 2750 m h z t o 75 mh z/v a t 3400 mh z (+33%, ?17%). v a r i a t io n s in t h es e p a ra met e rs c h a n g e t h e lo o p b a ndwi d t h . t h is in t u r n can a f fe c t st ab i l i t y an d lo ck t i m e . by cha n g i n g t h e p r og ra mma b l e i cp , i t is p o ssib le t o get co m p en s a - t i o n fo r t h es e v a r y in g lo o p co n d i t io n s and ens u r e t h a t t h e lo o p i s a l w a y s op e r at i n g cl o s e to opt i m a l c o n d i t i ons .
adf4110/adf4111/a df4112/adf4113 rev. c | page 24 of 28 v dd v p av dd dv dd adf4110 adf4111 adf4112 adf4113 v p 4.7k ? vco v cc gnd 18 ? 18 ? 18 ? 100pf 100pf rf out ref in 51 ? 100pf 100pf d n g p c d n g a d n g d rf in a rf in b decoupling capacitors and interface signals have been omitted from the diagram to increase clarity. r set cp ce power-down control v dd s in d gnd loop filter adg701 fref in 1 8 7 15 16 2 6 5 9 4 3 10 03496-0-040 f i gure 35. l o c a l o s cil l a to r s h utd o wn circuit v dd v p av dd dv dd adf4113 v p 2.8nf 680 ? 130pf 3.3k ? 19nf m3500-2235 v cc 18 ? 18 ? 18 ? 100pf 100pf rf out 1000pf 1000pf 51 ? ref in muxout lock detect 51 ? 100pf 100pf d n g p c d n g a d n g d rf in a rf in b ce clk data le s u b l a i r e s e l b i t a p m o c - i p s decoupling capacitors on av dd , dv dd , v p of the adf4113 and on vcc of the m3500-2250 have been omitted from the diagram to aid clarity. r set cp 4.7k ? 12v v_tune gnd 20v 1k ? ad820 3k ? out fref in 3 4 9 5 6 14 2 1 8 7 15 16 03496-0-041 f i gure 36. wideb a n d p h ase - l o ck ed l o op
adf4110/adf4111/a df4112/adf4113 rev. c | page 25 of 28 direc t c o n v ersion m o dul a t o r i n s o me a p p l i c at i o ns , a d i re c t c o n v e r s i on arch it e c tu re c a n b e us e d in b a s e st a t io n t r a n sm i t t e rs. f i gur e 37 sh o w s t h e com b ina - t i on av ai l a bl e f r om a d i to i m pl e m e n t t h i s s o lut i on . the cir c ui t dia g ra m sh o w s the ad9761 bein g us ed wi t h the ad8346. th e us e o f d u al in teg r a t ed d a cs s u ch as the ad9761 wi t h sp ecif ie d 0.02 db an d 0. 004 db ga in an d o f fs et ma t c hin g char ac te r i st ic s e n su re s mini m u m e r ror c o n t r i bu t i on ( o ve r t e m p era t ur e) f r o m t h is p o r t io n o f t h e sig n al cha i n. the lo cal os cil l a t o r (l o) is im p l em en t e d usin g t h e ad f4113. i n this cas e , t h e o s c 3b1-13m0 p r o v ides th e s t a b le 13 mh z r e f e r e n c e f r eq uen c y . th e sys t em is desig n e d f o r a 200 kh z c h a n n e l s p ac in g a nd an o u t p u t c e n t er f r eq uen c y o f 1960 mh z. t h e t a r g e t ap p l i c at i o n i s a w c d m a b a s e s t at i o n t r a n s m i t t e r . t y p i cal p h as e no is e p e r f o r ma nce f r o m this l o is ?85 db c/h z a t a 1 k h z o f fs et. the l o p o r t o f th e ad8346 is dr i v en in sin g le-en d e d fas h ion. l o in is ac-co u p l ed t o g r o u nd wi t h t h e 100 pf ca p a c i t o r ; l o ip is dr i v en thr o ug h the ac co u p ling ca p a c i t o r f r o m a 50 ? s o ur c e . an lo dr i v e l e vel o f b e tw e e n ? 6 dbm and ?12 dbm is r e q u ir e d . the cir c ui t o f f i gur e 37 g i v e s a typ i cal leve l o f ?8 db m. the rf o u t p u t i s desig n e d t o dr i v e a 50 ? lo ad b u t m u st b e ac- co u p le d as sh ow n in f i gur e 37. i f t h e i and q i n p u ts a r e dr i v e n in quadr a t u r e b y 2 v p-p sig n a l s, t h e r e su l t ing o u t p ut p o w e r is a r o u n d ?10 dbm. r set adf4113 18 ? 100pf 18 ? ref in 100pf rf in a rf in b cp serial digital interface tcxo osc 3b1-13m0 100pf 620pf 3.9k ? 3.3k ? 9.1nf 4.7k ? 18 ? 100pf rf out power supply connections and decoupling capacitors are omitted from diagram to increase clarity. ad9761 txdac refio fs adj modulated digital data qoutb iouta ioutb qouta ad8346 loin loip vout 100pf 100pf 2k ? 51 ? 910pf vco190-1960t ibbp ibbn qbbp qbbn low-pass filter low-pass filter 03496-0-042 f i g u re 37. d i r e c t convers i on t r ans m it ter s o lut i on
adf4110/adf4111/a df4112/adf4113 rev. c | page 26 of 28 interf a c i n g the ad f4110 f a mil y has a sim p le s p i? co m p a t i b le s e r i al in t e r - face f o r wr i t in g t o th e de vice . s c lk, s d a t a, and le co n t r o l t h e da ta tra n sf e r . w h en la t c h e n a b le (l e) g o e s h i gh , th e 24 b i ts th a t h a v e been c l ock e d in t o th e in p u t r e gi s t e r o n ea ch ri s i n g ed g e o f sclk g e t t r an sfer r e d t o t h e a p pr o p r i a t e la t c h. s e e f i gur e 2 fo r th e tim i n g di a g ra m a n d t a b l e 5 f o r th e la t c h tr u t h ta b l e . the max i m u m a l lo wa b l e s e r i a l clo c k ra te is 20 mh z. t h is m e a n s th a t th e m a xi m u m u p da t e ra t e pos s i b le f o r th e de v i ce i s 833 kh z, o r o n e u p da te ever y 1.2 s. this is cer t a i nl y m o r e tha n a d eq ua t e f o r sys t e m s tha t ha v e typ i cal loc k tim e s i n t h e h u ndr e d s o f mi cr o s e c o n ds. adu c 812 i n t e r f a c e f i gur e 38 s h o w s th e in t e r f ace betw een t h e ad f 4110 fa mil y an d th e aduc812 m i cr oc o n v e r t er?. s i n c e t h e ad uc812 is bas e d o n a n 8051 co r e , this in t e r f ace can be us e d wi t h an y 8051 bas e d micr o c o n t r ol ler . the micr oc o n v e r t er is s e t u p fo r s p i mas t er m o de wi t h cph a = 0. t o ini t ia t e t h e op era t ion, th e i / o p o r t dr i v in g le is b r o u g h t lo w . e a c h la t c h o f th e adf4110 fa mil y n e e d s a 24-b i t w o r d . this is ac co m p lish e d b y wr i t in g thr e e 8-b i t b y t e s f r o m t h e micr oc o n v e r t e r t o t h e de vice . w h en t h e t h ir d b y te h a s b e e n w r i t te n, t h e l e i n put s h ou l d b e brou g h t h i g h to co m p let e t h e tr a n sf er . w h en p o w e r is f i rs t a p p l ie d t o t h e ad f4110 famil y , thr e e wr i t es are ne e d e d ( o ne e a ch to t h e r c o u n te r l a tc h , n c o u n te r l a tc h , a nd ini t ializa tion l a t c h) f o r the o u t p u t t o b e com e ac t i v e . i/o p o r t lin e s on the adu c 812 a r e als o us ed t o co n t r o l p o w e r - do wn (ce i n p u t ) , a n d to dete c t l o ck (mu x out co nf igur e d as lo c k det e c t an d p o l l ed b y th e p o r t in p u t). w h en t h e adu c 812 is o p era t in g in t h e m o de des c r i b e d abo v e, th e maxim u m s c l o ck ra te o f th e aduc812 is 4 mh z. this m e a n s th a t th e m a xi m u m ra t e a t w h i c h t h e o u t p u t f r eq ue n c y ca n be c h a n g e d is 166 kh z. sclock mosi i/o ports aduc812 sclk sdata le ce muxout (lock detect) adf4110 adf4111 adf4112 adf4113 03496-0-043 f i gur e 3 8 . aduc812 to adf411 0 f a mil y int e r f a c e a d s p -218 1 inter f a c e f i gur e 39 s h o w s th e in t e r f ace betw een t h e ad f 4110 fa mil y an d th e ads p -21xx dig i t a l sig n al p r o c es s o r . the ad f4110 fa mil y n e e d s a 24- b i t s e r i a l w o r d fo r e a ch l a t c h wr i t e. the e a siest wa y t o acco m p lish t h is usin g t h e a d s p -21xx fa m i ly is t o us e t h e au t o b u f f e r e d t r a n s m i t m o d e o f o p e r at i o n w i t h a l t e r n at e f r am i n g . t h i s prov i d e s a me ans for t r ans m i t t i n g an e n t i re bl o c k o f se ri al d a ta bef o r e a n i n t e rr u p t i s g e n e ra t e d . sclk dt i/o flags adsp-21xx sclk sdata le ce muxout (lock detect) adf4110 adf4111 adf4112 adf4113 tfs 03496-0-044 f i gur e 3 9 . adsp -21xx t o adf411 0 f a mi l y int e r f a c e s e t u p t h e w o r d le n g th f o r 8 b i ts a n d use th r e e m e m o r y lo ca tion s f o r eac h 24-b i t w o rd . t o p r og ra m each 24-b i t la t c h, s t o r e t h e t h r e e 8 - b i t b y t e s, enab le t h e a u t o b u f f er e d mo de , and t h e n wr i t e t o t h e t r a n smi t r e g i s t er o f t h e ds p . this last o p era- t i o n ini t ia t e s t h e a u t o b u f f er t r a n sfer . pcb desig n guideline s for chip sc ale pa c k a g e the lan d s on t h e chi p s c ale p a cka g e (c p - 20) a r e r e c t a n gu la r . the p r in te d cir c ui t b o a r d p a d for t h es e sh o u ld b e 0.1 mm lo n g e r th a n th e pa c k a g e la n d len g th a n d 0. 05 m m w i d e r th a n t h e p a cka g e land w i d t h. th e l a nd sh o u ld b e ce n t er e d o n t h e p a d . this ens u r e s t h a t t h e s o lder jo i n t si ze is maximize d . the b o t t o m o f t h e chi p s c ale p a cka g e has a ce n t ral t h er mal p a d . the t h er mal p a d o n t h e p r in t e d cir c ui t b o a r d sh o u ld b e a t le ast a s la r g e a s th i s exposed pa d . on th e p r i n t e d ci r c ui t boa r d , th e r e s h o u ld b e a cle a ra n c e o f a t le as t 0.25 mm b e tw e e n t h e t h er mal p a d an d t h e in ner e d ges o f t h e p a d p a t t er n. thi s en sur e s t h a t shor t i ng i s a v oi d e d. ther mal v i as ma y b e us e d on t h e p r i n t e d cir c ui t b o a r d t h er mal p a d t o im p r o v e t h er mal p e r f o r ma nce o f t h e p a cka g e . i f vi as a r e used , th ey s h o u l d b e in co r p o r a t ed in th e th e r m a l pa d a t 1. 2 mm p i t c h g r id . th e v i a diamet er sho u ld b e b e tw e e n 0.3 mm an d 0.33 mm, an d t h e via b a r r e l s h o u ld be pla t ed wi t h 1 oz. co p p er to plu g t h e v i a. the us er sho u ld co nne c t t h e p r i n te d cir c ui t b o ar d t h er ma l p a d to a g nd .
adf4110/adf4111/a df4112/adf4113 rev. c | page 27 of 28 outline dimensions 1 20 5 6 11 16 15 bottom view 10 2.25 2.10 sq 1.95 0.75 0.55 0.35 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0. 80 m a x 0.65 typ 0.05 max 0.02 nom 1.00 0.85 0.80 seating plane pin 1 indicator top view 3.75 bs c s q 4.0 bsc sq coplanarity 0.08 0.60 max 0.60 max 0 . 2 5 mi n compliant to jedec standards mo-220-vggd-1 f i gure 40. 2 0 -l ead l e ad f r a m e ch ip s c a l e p a ck ag e [lfcs p ] (c p - 2 0 - 1 ) di me nsio ns sho w n i n mi ll im e t e r s 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153ab f i gure 41. 1 6 -l ead thin shr i nk s m a l l o u tline p a ckage [ t ssop ] (ru - 16) di me nsio ns sho w n i n mi ll im e t e r s
adf4110/adf4111/a df4112/adf4113 rev. c | page 28 of 28 orderi ng guide model temperature r a nge package descri ption package option adf4110bru C40c to +85c thin sh rink small outline package ru-16 adf4110bru-r eel C40c to +85c thin sh rink small outline package ru-16 adf4110bru-r eel7 -40c to +85c thin sh rink small outline package ru-16 adf4110bcp C40c to +85c lead frame chip scale package cp-20 adf4110bcp -r eel C40c to +85c lead frame chip scale package cp-20 adf4110bcp-re el7 C40c to +85c lead frame chip scale package cp-20 adf4111bru C40c to +85c thin sh rink small outline package ru-16 adf4111bru-r eel C40c to +85c thin sh rink small outline package ru-16 adf4111bru-r eel7 C40c to +85c thin shrink small outline package ru-16 adf4111bcp C40c to +85c lead frame chip scale package cp-20 adf4111bcp-re el C40c to +85c lead frame chip scale package cp-20 adf4111bcp-re el7 C40c to +85c le ad frame chip scale package cp-20 adf4112bru C40c to +85c thin sh rink small outline package ru-16 adf4112bru-r eel C40c to +85c thin shrink small outline package ru-16 adf4112bru-r eel7 C40c to +85c thin shrink small outline package ru-16 adf4112bruz 1 C40c to +85c thin shrink small outline package ru-16 adf4112bruz 1 -reel C40c to +85c thin shrink small outline package ru-16 adf4112bruz 1 -reel7 C40c to +85c thin shri nk small outline package ru-16 adf4112bcp C40c to +85c lead frame chip scale package cp-20 adf4112bcp-re el C40c to +85c lead frame chip scale package cp-20 adf4112bcp-re el7 C40c to +85c le ad frame chip scale package cp-20 adf4113bru C40c to +85c thin sh rink small outline package ru-16 adf4113bru-r eel C40c to +85c thin shrink small outline package ru-16 adf4113bru-r eel7 C40c to +85c thin shrink small outline package ru-16 adf4113bruz 1 C40c to +85c thin shrink small outline package ru-16 adf4113bruz 1 -reel C40c to +85c thin shrink small outline package ru-16 adf4113bruz 1 -reel7 C40c to +85c thin shri nk small outline package ru-16 adf4113bcp C40c to +85c lead frame chip scale package cp-20 adf4113bcp-re el C40c to +85c lead frame chip scale package cp-20 adf4113bcp-re el7 C40c to +85c lead frame chip scale package cp-20 adf4113bchip s C40c to +85c die eval-adf4112 e b 1 e v a l u a t i o n boar d eval-adf4113 e b 1 e v a l u a t i o n boar d eval-adf4113 e b 2 e v a l u a t i o n boar d eval-adf411 xe b 1 e v a l u a t i o n b o a r d 1 z = pb-free part. purch a se of li c e n s e d i 2 c com p on en t s o f an a l og d e vi ces or on e of i t s subli c en s e d as soci a t ed c o m p a n i e s con v eys a li cen s e for t h e purch a ser un der t h e ph i li p s i 2 c p a te nt rights to us e the s e co mpo n e nts in an i 2 c sy st em , provi d e d t h a t t h e syst em c o n f orm s t o t h e i 2 c stand a rd speci f ication as d e f i ned by phil ips . ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . c03496C0 C 3/04(c)

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